1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory, and a driving method of the same.
2. Description of the Related Art
Generally, a memory cell in an EEPROM (Electrically Erasable Programmable Read Only Memory) or a Flash memory is composed of a MOS (Metal Oxide Semiconductor) transistor shown in FIG. 1. As shown in FIG. 1, a source 302 and a drain 303 are formed in the surface of a semiconductor substrate 301 in the memory cell. A floating gate 305 is formed on the semiconductor substrate 301 through a tunnel oxide film 304. In addition, a control gate 307 is formed on the floating gate 305 through an insulating film 306. For instance, in “Flash Memory Guide Book, Chapter 2”, (URL: http://flash.iqnet.co.jp/product/guide/duide02.html, retrieved on the Mar. 4, 2004)>, the following conventional technique is described. That is, an n-type source and an n-type drain are formed in a p-type silicon substrate. A floating gate is formed on the p-type silicon semiconductor substrate through a tunnel oxide film. Moreover, a control gate is formed on the floating gate through an insulating film. Thus, a MOS transistor is formed.
FIG. 2 is a diagram showing an array of a NOR type flash memory for one bit line and one word line. Drains of a plurality of memory cells 401, 402, and 403 are commonly connected with a same bit line 202. In such a configuration, for instance, it is supposed that data has been written in the memory cell 401, a writing operation is being carried out to the memory cell 402, and no data is written in the memory cell 403. In this case, each of the memory cells 401, 402, and 403 is connected to a word line extending in a row direction together with other memory cells.
FIGS. 3A to 3C are diagrams showing electric charge stored states of each memory cell of the NOR type flash memory. FIG. 3A shows the electric charge stored state of the memory cell 402 in which data is being written. FIG. 3B shows the electric charge stored state of the memory cell 403 in which no data is written. FIG. 3C shows the electric charge stored state of the memory cell 401 in which data has been written. Here, when data is written in the memory cell 402, the bit line 202 is selected and the voltage of 3V to 5V is applied to the bit line 202. Also, as shown in FIG. 3A, the voltage of 9V is applied between the control gate 307 and the drain 303 in the memory cell 402, so that channel hot electrons 501 are generated. The channel hot electrons 501 are injected into the floating gate 305 of the memory cell 401 because of the gate voltage and stored therein. At this time, as shown in FIG. 2, the bit line voltage is applied to the drains of memory cells 401 to 403 connected with the same bit line 202. However, the gate voltage is not applied to the memory cells 401 and 403. In this case, since the bit line voltage to be applied to the drains of the memory cells 401 to 403 is a relatively high voltage (3V to 5V), an interband leak between the drain and the channel region is generated, as shown in FIGS. 3B and 3C. Although holes 502 are generated at this time, the holes 502 causes no problem in the memory cell in which no data is written. However, in the memory cell 401 in which data has been written, the holes 502 are attracted by the negative electric charge stored in the floating gate 305, and injected into the tunnel oxide film 304. As a result, the tunnel oxide film 304 is damaged.
Also, the tunnel oxide films of other memory cells 404 are damaged, which are connected with the same word line 201 as the memory cell 402. The bit line voltage is not applied to the other memory cells 404, which are connected with the same word line 201 as the memory cell 402, but only the word line voltage is applied. That is, only the gate voltage is applied. As a result, the electrons are injected into the tunnel oxide film 304 so as to be damaged.
FIG. 4A is a diagram showing a memory cell array of the flash memory. FIG. 4B is a schematic diagram showing an outline of the array with 512 memory cells for each bit line. In the flash memory, when the electrons are excessively drawn out from the floating gate in an erasing operation, the floating gate is changed into a positive charge state, and the threshold of the memory cell transistor becomes negative. As a result, the operation of the transistor cannot be carried out normally, that is, an excessive erasing is caused. In order to prevent the excessive erasing, a writing operation is carried out to all the memory cells before the erasing operation, to stop the erasing operation in the most preferable erasure level. In such a writing operation before the erasing operation, the writing operation is generally carried out in a direction from the most significant bit (uppermost) address to the least significant bit (lowermost) address, namely, the address ($000) to the address ($1FF), as shown in FIG. 4A. In FIG. 4B, the writing operation is carried out in order from the memory cell 1, to the memory cell 2, the memory cell 3, . . . , and the memory cell 512. That is to say, the writing operation always starts from the memory cell 1, and stops at the memory cell 512.
By the way, as electronic equipment of multi-function, high performance, and miniaturization in size has been developed, it is required that a memory should be further has a large storage capacity and a low-cost performance. In order to satisfy these requirements, two solutions can be proposed. One is to achieve the high integration by making the memory cell minute. The other is to increase the memory capacity for one memory cell by using a multi-value technology. The multi-value technology will be described below.
FIGS. 5A and 5B are diagrams showing a relation of the number of bits and the thresholds of the memory cell. The memory is usually operated in a binary manner. That is, as shown in FIG. 5A, 1-bit data is stored depending on whether the 1-bit data is “1” or “0”. On the other hand, for instance, in the flash memory using the 4-value technology, the “high”, “middle”, “low”, and “initial” thresholds of the memory cell are set to “11”, “10”, “01”, and “00” of binary data. Therefore, one memory cell can store 2-bit data. Recently, numerous investment is needed for miniaturization of the memory cell. For this reason, the importance of the multi-value technology has been increased to make the memory capacity twice or more in the same integration.
In this way, in the EEPROM and the flash memory, the electric charge is stored in the floating gate 305 as shown in FIG. 1, to control the threshold of the memory cell transistor. In the binary technology, the threshold of the memory cell has only two states. However, in the 4-value technology, the memory cell must have four states. Therefore, the threshold of the memory cell transistor must be accurately controlled strictly. As a result, higher reliability is required for each memory cell.
However, the above-mentioned conventional nonvolatile memory has the following problems. As shown in FIG. 3C, the holes generated through the interband leakage between the drain and the channel region are attracted to the negative electric charge stored in the floating gate 305. As a result, a hole injection stress is generated, when the holes are injected into the tunnel oxide film. Thus, the tunnel oxide film receives serious damage.
In case of the flash memory shown in FIG. 4A, the writing operation before the erasing operation always starts from the memory cell 1 and ends at the memory cell 512. For this reason, when the writing operation is carried out to all the memory cells connected to the same bit line, the memory cell 1 receives the above-mentioned hole injection stress which is caused through the writing operation to the 511 remaining memory cells connected to the same bit line as the memory cell 1. On the other hand, the memory cell 512 does not receive the hole injection stress since the writing operation is carried out last. The writing/erasing operations are repeated tens of thousands of times or more in the flash memory. Therefore, the damage is compiled each time the writing/easing operation is repeated and becomes serious damage that should not be disregarded.
In this way, the hole injection stress caused due to the high voltage of the drain is applied nonuniformly depending on the position of the memory cell on the same bit line, since the order of the write addresses is always same. For instance, in FIGS. 3A to 3C, it is supposed that the writing/erasing operations are repeated 10,000 times and the writing operation is carried out to all the 512 memory cells on same bit line. In this case, under the above-mentioned condition, the memory cell 1 of the address ($000) receives the hole injection stress of “5,110,000 times*(an average write time per one memory cell)”. On the other hand, the memory cell 512 of the address ($1FF) receives no hole injection stress. It should be noted that a problem of electron injection stress is caused in the memory cells on a same word line, similar to the above.
In conjunction with the above description, a nonvolatile semiconductor memory device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 9-97884). In this conventional example, an impurity region of a second conductive type is formed in a semiconductor substrate of a first conductive type. A first insulating film is formed on the surface of the impurity region of the second conductive type, and an electric floating gate electrode is formed on the first insulating film. A control electrode is formed on the floating gate electrode through a second insulating film to overlap the floating gate in at least a part. A first source (drain) region of the first conductive type is formed in the impurity region of the second conductive type, and a second source (drain) region of the second conductive type is formed in the first source (drain) region of the first conductive type. A drain (or source) region of the first conductive type is formed in the impurity region of the second conductive type. In a write operation, electrons supplied from the semiconductor substrate of the first conductive type are accelerated by a depletion layer generated between the impurity region of the second conductive type and the first source (or drain) region of the first conductive type to be injected into the floating gate. Also, in an erasing operation, holes supplied from the impurity region of the second conductive type are accelerated by the depletion layer generated between the first source (drain) of the first conductive type (or) and the second source (drain) region of the second conductive type to be injected into the floating gate.
Also, a nonvolatile semiconductor memory device is disclosed in Japanese Laid Open Patent Application (JP-P2002-118184A). In this conventional example, a channel forming region of an N-type semiconductor is put between two source/drain regions of the p-type semiconductor. A gate insulating film is provided onto the channel forming region, and a gate electrode is provided onto the gate insulating film. An electric charge storage section is formed in a region opposing to the channel forming region and in the gate insulating film distributedly into the direction of the film thickness. A channel is formed in the channel forming region, and hot holes generated with electric field in the channel are injected into the electric charge storage section for a write operation. Also, hot electron are generated due to interband tunnel current between the source/drain regions, and are injected into the electric charge storage section holding the electrons for an erasing operation.